The present invention relates generally to integrated circuits and in particular the present invention relates to supply input levels for integrated circuits.
Manufacturers of electronic devices, such as handheld products, are under constant pressure to reduce power consumption. One technique used to reduce power is to reduce operating voltage levels. Further, a reduction in the operating voltage levels of data buses can provide significant reductions in power consumption. That is, power dissipated during a transfer of data is proportional to the capacitance of the bus and the square of the switched voltage levels (P=kCV2). The V2 term indicates that any reduction in operating voltage for the bus has a dramatic change in the power consumption.
Reducing data bus operating voltages can reduce the bandwidth of the bus. That is, the input/output (I/O) circuitry coupled to the data bus typically exhibits reduced performance at lower operating voltages. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an integrated circuit that can have a reduced power consumption while still allowing for higher data bandwidth.
The above-mentioned problems with integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a communication system comprises a controller, a data communication bus, and a memory device coupled to the controller via the data communication bus. The memory device comprises an input circuit coupled to the data communication bus to detect a voltage signal on the bus. The input circuit has first and second voltage threshold settings that are selected based on externally provided commands from the controller.
In another embodiment, a memory device comprises an input connection to receive input voltage signals, an input circuit coupled to the input connection and comprising a threshold voltage detection circuit, and command control circuitry to change a threshold voltage detection level of the input circuit in response to an externally provided command sequence.
A synchronous non-volatile memory device comprises a clock input signal connection, a clock enable signal input connection (CKE), a data input connection to receive data input voltage signals, and an input circuit coupled to the data input connection and comprising a threshold voltage detection circuit. Command control circuitry changes a threshold voltage detection level of the input circuit in response to an externally provided command and a power-down operation.
A method of operating a memory device comprises instructing the memory to change an input signal threshold voltage in response to receiving a synchronization signal, changing a supply voltage provided to the memory device, receiving the synchronization signal after the supply voltage is changed, and changing the input signal threshold voltage.